The performance improvement of conventional processor has begun to stagnate in recent years. Because of this, researchers are looking for new possibilities to improve the performance of computing systems. Heterogeneous systems turned out to be a powerful possibility. In the context of this talk, a heterogeneous system consists of a software-programmable processor and a FPGA based configurable hardware accelerator.
Due to their increased complexity, it is more complicated to develop applications for heterogeneous systems than for conventional systems based on a software-programmable processor. For programming the software and hardware parts, different languages have to be used and additional specialised hardware-knowledge is required. Both factors increase the development cost.
This work presents the compiler framework Nymble which allows to program a heterogeneous system with only a single high-level language. In the high-level language the developer only has to select which parts of the application should be executed in hardware. Nymble then generates a program for the software-processor, the configuration of the hardware, and all interfaces between software and hardware.
To hide long memory access latencies, this talk presents an execution model which allows the simultaneous execution of multiple threads in a single accelerator. Additionally, the model enables threads to be dynamically reordered at specific points in the common accelerator pipeline. This capability is used to let other (non-waiting) threads overtake a thread which is waiting for a memory access. Thus, these other threads can execute their calculations independently of the waiting thread to bridge the latency of memory accesses.
The presented execution model dynamically spreads multiple threads over the pipeline. This results in a higher utilisation of the resources by using resources more effectively. Furthermore, the simultaneous execution of multiple threads can achieve similar throughput as multiple copies of a single-threaded accelerator running in parallel.
It makes it possible to combine the improved throughput of multiple copies with the increased efficiency of simultaneous threads in a single accelerator. Thread reordering allows the new model to be effectively used with a cached shared-memory.
In comparison, between four copies of a single-threaded accelerator and a multi-thread accelerator with four thread (both created by Nymble), a resource efficiency of up to factor 2.6x can be achieved. At the same time, four simultaneous threads can be up to 4x as fast as four threads executed consecutively on a single accelerator. Compared to other, more optimised compilers, Nymble can still achieve up to 2x faster runtime with 1.5x resource efficiency.

The inevitable end of Moore’s law motivates researchers to re-think many of the historical architectural decisions. Among these decisions we find the representation of floating-point numbers, which has remained unchanged for nearly three decades. Chasing better performance, lower power consumption or improved accuracy, researches today are actively searching for smaller and/or better representations. Today, a multitude of different representations are found in the specialized (e.g. Deep-Learning) applications as well as for general-purpose applications (e.g. POSITs).
However, despite their claimed strengths, alternative representations remain difficult to evaluate empirically. There are software approaches and emulation libraries available, but their sluggishness only allows the smallest of inputs to be evaluated and understood.
POSIT is a new numerical representation, introduced by professor John Gustafson in 2017 as a candidate to replace the traditional IEEE-754 representation. In this talk I will present my experience in designing, building and accelerating the POSIT numerical representation on Field-Programmable Gate Arrays (FPGAs). I will start by briefly introducing the POSIT representation, show its hardware implementation details, reasoning around their trade-offs (with respect to IEEE-754) and conclude the presentation with small use-cases and their measured/obtained performance.

This talk will consist of two parts. In part I, I'll overview the current status of FDPS (Framework for Developing Particle Simulator). FDPS provide an easy and highly efficient way to develop parallel program for particle-based simulations, through extensive use of metaprogramming. It takes the definitions of particle class and particle-particle interaction function as input, and generates high-performance parallel libraries for domain decomposition, particle exchange and interaction calculation. Using these functions, application programmers can develop their own parallel programs, without spending much time to write and debug parallel code written in MPI. In fact, an application program written using FDPS functions contain no MPI calls and yet run on single-core, multiple cores using OpenMP or multiple nodes using MPI (or hybrid OpenMP-MPI) without the need of the change in the source code. After the initial release of FDPS in 2015, we have added many additional functionalities and performance improvement, which I'll overview in this talk. In the second part, I'll discuss how one can design the processors architecture which is "optimal" in some well-defined meaning.

We will give a talk on the recent achievements and future plans in the computational molecular science research team. In particular, we will introduce materials design of hole-transporting materials (HTMs) for perovskite solar cells. In this study, the efficient search of optimum HTMs was achieved by applying machine learning techniques. We employed the deep neural network to predict the power conversion efficiency of perovskite solar cells with HTMs by utilizing molecular descriptors as input features. We also employed the Gaussian process regression to evaluate the acquisition function in Bayesian optimization and implement uncertainty and reliability to the prediction model. Discrete particle swarm optimization was applied to tackle the optimization problem in the vast chemical space. In addition, we will introduce the future development of the solar-cell simulator based on the dynamic Monte Carlo approach with the first-principles calculation.

The state-of-the-art topology for modern supercomputers are Folded Clos networks, a.k.a. Fat-Trees. The node count in these massively parallel systems is steadily increasing. This forces an increased path length, which limits gains for latency-sensitive applications. A novel, yet only theoretically investigated, alternative is the low-diameter HyperX. To perform a fair side-by-side comparison between a 3-level Fat-Tree and a 12x8 HyperX, we constructed the world’s first 3 Pflop/s supercomputer with these two networks. We show through a variety of benchmarks that the HyperX, together with our novel communication pattern-aware routing, can challenge the performance of traditional Fat-Trees.

Communication hiding is a well-known approach for realizing the higher performance of applications. Especially, to get ideal parallel performance with strong scaling, effective communication hiding essential. However, in some applications, we can not hide communications as we expect. In this study, we modelize communication hiding for each application and system. By this model, we judge the communication hiding is useful or not. In this talk, we discuss the validity of the model with general stencil problems.

Whole-brain simulation allows us to understand full interactions among neurons and helps elucidate brain function and disease. However, it has not been realized due to the insufficient computational power of current supercomputers and lack of experimental data of the brain. In this study, we propose an efficient and scalable parallelization method for whole-brain simulation executed on next-generation supercomputers. We focus on the biological features of the brain that major brain parts of the cortex and cerebellum form layered sheet structure with local-dense and remote-sparse connections. To exploit the biological features, our proposed method combines tile-partitioning method and communication method using synaptic transmission delay. Our proposed method showed good weak scaling performance for simulation of the cortex, cerebellum, and cortico-cerebello-thalamo-cortical circuits on the K computer. These results suggest that the size of the model may scale to human brain size on Fugaku computer. The whole-brain simulation on next-generation supercomputers may lead to a new paradigm of brain research.