R-CCS Cafe 第273回（2024年11月15日）

Title:
Quantum Error Correction Core Implementation on FPGA: Systolic Array and Reduction Tree Design
Abstract:
This work presents the design and implementation of a Quantum Error Correction (QEC) core on an FPGA platform, aimed at improving the reliability of quantum computing systems through real-time error correction. The core integrates a scalable systolic array of processing elements (PEs), a reduction tree for contact notice serialization, and a final matching unit that efficiently matches error patterns using a bloom filter. The design supports various code distances (D) and measurement rounds (R), allowing adaptability across different quantum error correction configurations.

The QEC core was synthesized on a Stratix 10 FPGA, demonstrating significant scalability while maintaining low resource usage. The performance of the hardware QEC core was verified against a golden model, and ongoing tests are aligning its behavior with expected quantum error correction performance. Future work will focus on further enhancing scalability by extending the implementation to an FPGA cluster, supporting higher code distances and additional measurement rounds, while maintaining low latency through efficient inter-FPGA communication.