R-CCS Cafe 第211回 第3部

Coarse-Grained Reconfigurable Arrays (CGRA) is an architecture that offers enough reconfigurability yet still provides ASIC-like performance. It is also an efficient architecture for accelerating dataflow computation. However, often a host CPU is still required for operations that cannot be handled efficiently in CGRA and other tasks. Therefore, an efficient task offloading mechanism between CPU and CGRA is important. In this ongoing research, we surveyed several commercially available CPU - Accelerator interconnects in the market. Based on the survey result, we look into the hardware structure and how it may affect the programmability aspect of the CGRA. We identified several key aspects: the internal state of the accelerator, host memory access, cache coherence, virtual memory, and concurrency control.