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Recent CPU architectures support wide SIMD instructions with extended vector lengths. As many operations can be executed in one instruction, high performance processing is expected. ARM has announced the Scalable Vector Extension (SVE), which is an extended SIMD instruction set. The most significant feature of SVE is uniform support for vector lengths from 128 bits to 2048 bits. It realizes Vector Length Agnostic programming which does not depend on vector length.
The Arm processor designed for the post-K supercomputer will be equipped with this SVE features for SIMD acceleration.
In this talk, I will introduce an overview of ARM SVE. Then, I examine the effect of vector length and hardware resources in the performance and the runtime power consumption of benchmarks with multiple vector lengths.