The continuous improvement in processing speed in high-performance computer systems has been enabled by transistor scaling known as Moore's law. However, this trend is predicted to end in the near future. It is vital to research and develop new, more efficient high performance architectures to continue realizing high performance computing systems. One of the ways to improve performance of computer systems in the post-Moore era is utilizing domain specific architectures. In this talk, we briefly introduce our recent research efforts on a domain specific architecture for graph processing. In this research, we focus on the edge-centric graph processing model and propose a dedicated cache architecture for exploiting data locality. We have evaluated our cache architecture by a light weight cache simulation and the results showed that it can reduce the number of LLC cache misses by up to 89.9%.
日時: 2020年1月14日（火）、13:40 - 14:20
場所: R-CCS 6階講堂
・講演題目：Performance Improvement by Domain Specific Architectures: A Case Study in Graph Processing