Recently, FPGA has been attracting attention as an alternative device to accelerate HPC applications. Data flow computing model is a popular abstraction of computing in both fine-grain and coarse-grain from decades, and this model is used as a programming model for FPGA such as Maxler DFE and SPGen (Stream Processor Generator). While it is a kind of “static” data flow model, it might be interesting to extend models by using “dynamic” data flow models as old dataflow architecture to handle the dynamic behavior of systems. On other hands, global programming models to integrate FPGA computing into parallel computing of host processors are also important. OpenMP task and target directives, which are recently introduced in OpenMP 4.5, can be extended to specify the interface to offloaded computation done by FPGA. And, the optimization for FGPA needs different metric such as hardware resources, which are very different from the optimization of CPU and GPU. In this talk, issues on programming models for FPGA accelerated HPC are presented.
日時: 2019年12月2日（月）、13:40 - 14:20
場所: R-CCS 6階講堂
・講演題目：Task-Parallelism and Dataflow: Programming models for FPGA accelerated HPC
・講演者：佐藤 三久（計算科学研究センター 副センター長／プログラミング環境研究チーム チームリーダー）