The continuous improvement in processing speed in high-performance computer systems has been enabled by transistor scaling known as Moore's law. However, this trend is predicted to end in the near future. It is vital to research and develop new, more efficient high performance architectures to continue realizing high performance computing systems. One of the missions of our team is to research and develop a next-generation high-performance computer architecture together with strategies to improve the power efficiency of exascale supercomputer systems. Our research focus includes non-von Neumann architectures, integrating next generation non-volatile memories and/or various types of accelerators into a general-purpose processor, acceleration of machine learning computations, and hybrid computing architectures that combine new and classical computing models. In this talk, we briefly introduce our recent research efforts on next generation high-performance architectures. We also present a power-aware resource management framework which have been developed by our JST CREST project. The developed framework controls power allocation among co-scheduled jobs to optimize total system throughput and power-efficiency within a given power constraint. We have tested this framework on a large-scale HPC cluster system with about 1000 compute-nodes and showed that it can successfully manage the system's power consumption.
日時: 2019年3月1日（金）、15:15 - 16:15
場所: R-CCS 6階講堂
・講演題目：Towards Next Generation HPC Architecture and its Power Management
・講演者：近藤 正章（次世代高性能アーキテクチャ研究チーム チームリーダー）