The 253rd R-CCS Cafe (Oct 6, 2023)

Title:
Recent activity in Computational Climate Study Research Team
Abstract:
Our team continues to develop SCALE as a climate/weather model library. This library has the capability to perform not only simulations but also subsequent data analysis. The latter has generally been done in serial computation, but in this library, such data analysis has also been parallelized to handle large data sets from large-scale simulations.
In this presentation, I will report on the progress of our research and development of SCALE according to recent activities.

Title:
Simulation of quantum computer and applications
Abstract:
Quantum information technologies are now expected to surpass classical ICT in the near future, and research and development has begun toward an integrated ICT system that combines classical and quantum functions. First step in this integration begins with a HPC system connected to a QPU with low latency. HPC not only controls QPU but also simulates the QPU allowing users to test and develop quantum applications beyond the available performance of the QPU. In my unit, I am working with Dr. Naoki Yoshioka to develop a QPU simulator called "braket" for "Fugaku" using the state vector method. In this talk, we will discuss the current state of this "braket" simulator and its application to quantum algorithm for material design.

Title:
At the Locus of Performance: Quantifying the Effects of Copious 3D-Stacked Cache on HPC Workloads
Abstract:
Over the last three decades, innovations in the memory subsystem were primarily targeted at overcoming the data movement bottleneck. In this talk, we focus on a specific market trend in memory technology: 3D-stacked memory and caches. We investigate the impact of extending the on-chip memory capabilities in future HPC-focused processors, particularly by 3D-stacked SRAM. First, we propose a method oblivious to the memory subsystem to gauge the upper-bound in performance improvements when data movement costs are eliminated. Then, using the gem5 simulator, we model two variants of LARC, a processor fabricated in 1.5 nm and enriched with high-capacity 3D-stacked cache. With a volume of experiments involving a board set of proxy-applications and benchmarks, we aim to reveal where HPC CPU performance could be circa 2028.