Session 12

Kazutomo Yoshii (ANL)
The performance progress of microprocessors has been driven by Moore’s law, doubling the number of transistors every 18 to 24 months. Such fabulous scaling will end soon. In the post-Moore era, the energy efficiency of com- puting will be a major concern. FPGA technology could be a key to maximizing the energy efficiency as well as performance. We present a summary of the ”Re-form” project and describe major challenges in the adoption of FPGA in high-performance computing.

Volodymyr Kindratenko (UIUC)
As far as 2008, High-Performance Reconfigurable Computing (HPRC) has been shown to ”achieve up to four orders of magnitude improvement in performance, up to three orders of magnitude reduction in power consumption, and two orders of magnitude saving in cost and size requirements compared with contemporary microprocessors when running compute-intensive applications based on integer arithmetic. ” (IEEE Computer, February 2008). Yet, HPRC continues to remain an obscure technology that has yet to realize its promise in the field of HPC. The most significant obstacle in realizing its potential is due to the lack of a programming model capable of extracting performance from the reconfigurable hardware that is simple enough to be accepted by the scientific computing community without the highly specialized knowledge of hardware design principles. While recent work on OpenCL based design flow is an attempt to address this challenge, in my opinion, it fails short of both being easy to use by the scientific computing community and being capable of extracting full FPGA performance.

Char: Leonardo Bautista Gomez (BSC)
Speakers:
Leonardo Bautista-Gomez (BSC) ”Introduction and objectives of the session”
Prasanna Balaprakash (ANL) ”Statistical analysis and predictive modeling for memory errors atexascale”
Osman Unsal (BSC) ”Methodologies for Memory Error Logging”

Correlation analysis of memory errors across multiple JLESC machines.