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R-CCS Cafe

R-CCS Cafe は、異分野融合のための足掛かりとして、計算科学研究センター(R-CCS)に集う研究者が井戸端会議的にざっくばらんに議論する場として、毎月2回程度予定しております。興味をお持ちの方は原則どなたでも参加可能です。

  • 目 的: 異分野間の壁を超えた研究協力を促進し、新しい学問分野の開拓を目指すため、 研究者間の情報交換・相互理解の場を提供し、研究協力のきっかけを作る。
  • 会 場:R-CCS 6階講堂もしくは1階セミナー室
  • 言 語:講演は日本語/英語、スライドは英語
  • その他:講演者は他分野の方にも理解できる発表を心掛け、参加者は積極的に質問しましょう。

第172回 第2部
日時: 2019年6月24日(月)、16:10 - 16:50
場所: R-CCS 6階講堂

・講演題目: An Introduction to Chemical Evolution of Galaxies
・講演者: 平居 悠(粒子系シミュレータ研究チーム、基礎科学特別研究員)
※発表・スライド共に英語

講演要旨: 詳細を見る

Galactic chemical evolution studies the enrichment histories of elements in the Universe. At the time of the Big Bang, the Universe consists of hydrogen, helium, and lithium. However, we are now living in the Universe with various kinds of elements. Most of the elements are synthesized in stars and distributed to space when a star ends its life.
These elements are inherited to the next generation stars. Elemental abundances of stars, therefore, reflect the nucleosynthetic histories in the galaxy. In the first part of this talk, I will show how the observed elemental abundances of stars in the Milky Way and satellite dwarf galaxies preserve information about their enrichment histories. In the Milky Way, the distribution of elements is different among old and new stars. The second part of this presentation focuses on the modeling of galaxy evolution. Hydrodynamic simulations of galaxies are presently a powerful tool to study galactic chemical evolution. It can self-consistently follow the formation of galaxies and the enrichment histories of elements. The last part discusses the enrichment of elements heavier than iron. The origin of elements synthesized by a rapid neutron-capture process such as europium, platinum, and gold is a long-standing problem in astronomy. Recently, binary neutron star mergers have been detected by the gravitational wave observations. I will show that they can be the source of such elements in galaxies. I will also present the future prospects of the studies of galactic chemical evolution.

第171回 第1部
日時: 2019年6月11日(火)、14:05 - 14:40
場所: R-CCS 6階講堂

・講演題目: A brief history of NEST on supercomputers
・講演者: Susanne Kunkel (PostDoc, The Norwegian University of Life Sciences)
※発表・スライド共に英語

講演要旨: 詳細を見る

NEST is a simulator for large-scale spiking neuronal networks with a history dating back to the late 1990s. The definition of what is considered a large-scale network has changed since as ever more powerful HPC facilities have become available. Contemporary supercomputers even provide the resources to represent brain-scale spiking neuronal networks. However, in order to enable neuronal simulators to exploit such resources, simulation code had to undergo fundamental design changes. Today, NEST works efficiently for a broad variety of models and on various platforms, from laptops to supercomputers. In my talk I will give an introduction to the NEST simulator and review the technological advances of the last years that have made NEST such an extremely scalable simulation tool.

第171回 第2部
日時: 2019年6月11日(火)、14:40 - 15:05
場所: R-CCS 6階講堂

・講演題目: Meeting the performance challenges of spiking network simulations on general purpose computers
・講演者: Jari Pronold (PhD student, The Jülich Research Centre, Germany)
※発表・スライド共に英語

講演要旨: 詳細を見る

Today’s extremely scalable simulation technology for spiking neuronal networks enables the representation of models of more than a billion of neurons and their connections using the entire K computer. However, the runtimes of the largest possible simulations carried out so far were too long to allow for observations of the network dynamics over long periods of time, and also small to medium-scale simulations typically run in far more than real-time. The performance challenges for spiking neuronal network simulators such as NEST on general purpose computers arise from the inherent sparse but broad connectivity between neurons and from the unpredictable neuronal spiking activity. In distributed simulations of spiking networks, this requires frequent communication of spike data, and on each compute node routing of the incoming spikes to the local targets. This entails irregular memory access and hence constitutes a major performance bottleneck, which is a problem that I will address in my talk. I will present recent developments in simulation technology that aim at meeting such performance challenges.

第170回 第1部
日時: 2019年6月7日(金)、13:00 - 13:55
場所: R-CCS 6階講堂

・講演題目: Working on the stable operation of the K computer
・講演者: 宇野 篤也(運用技術部門 システム運転技術ユニット ユニットリーダー)
※発表・スライド共に英語

講演要旨: 詳細を見る

The system operation and development unit has operated the K computer for more than 7 years. One of our important missions is operating the K computer stably. During the operation of the K computer, we have encountered some problems related to the file system, the job scheduling, the power consumption or etc. In this talk, I introduce our approaches to these problems for the stable operation of the K computer.

第170回 第2部
日時: 2019年6月7日(金)、13:55 - 14:50
場所: R-CCS 6階講堂

・講演題目: Systemization of performance optimization technique
・講演者: 南 一生(運用技術部門 チューニング技術ユニット ユニットリーダー)
※発表・スライド共に英語

講演要旨: 詳細を見る

Modern supercomputers are highly parallel machine combining inter-nodes process parallelism and inter-core thread parallelism. And the memory hierarchy including the cache in the node is also complicated. On the other hand, applications that run on supercomputers cannot fully utilize the performance of hardware unless high parallelization and individual node tuning are performed according to that hardware.Therefore, the two points“programming conscious of parallelism” and “programming conscious of execution performance”are essential techniques for users, researchers, and programmers who use the present supercomputers equipped with tens of thousands of processors and containing various enhancements and new functions. Here, we call the technique as the performance-optimizing techniques to application programs. Performance optimization of application is not always done by the application developer. It is difficult to interpret applications developed by others, evaluate their performance, discover problems, and solve problems. To systemize of the techniques of performance optimization will provide useful information for engineers and researchers who want to optimize the execution performance of applications. In this talk, I will talk about systemization of the techniques of performance optimization for single CPUs and high parallelism. Specifically, the following content is included.
-Classification of applications from the viewpoint of single CPU performance.
-Explain of busy time.
-Relationship of busy time and performance.
-Relationship of busy time and classification of applications.
-Relationship of busy time and performance tuning.
-Maximum performance estimation when busy time depends only on bandwidth.
-Accumulation of tuning techniques each application classification.
-Classification of problem regarding high parallelism.
-Accumulation of tuning techniques each problem classification.

第169回
日時: 2019年5月31日(金)、15:00 - 16:10
場所: R-CCS 6階講堂

・講演題目: Statistical emulation to quantify uncertainties in tsunami modelling using high performance computing
・講演者: Serge Guillas (Professor, University College London)
※発表・スライド共に英語

講演要旨: 詳細を見る

In this talk, we present solutions to the investigation of uncertainties in tsunami impacts in three settings.
First, we consider landslides as a source of tsunamis from the Indus Canyon in the Western Indian Ocean. We employ statistical emulation, i.e. surrogate modelling, to efficiently quantify uncertainties associated with slump-generated tsunamis at the slopes of the canyon. We simulated 60 slump scenarios to train the emulator and predict 500,000 trial scenarios in order to study probabilistically the tsunami hazard over the near field. The results show that the most likely tsunami amplitudes and velocities can potentially impact vessels and maritime facilities. We demonstrate that the emulator-based approach is an important tool for probabilistic hazard analysis since it can generate thousands of tsunami scenarios in few seconds, compared to days of computations on High Performance Computing facilities for a single run of the dispersive tsunami solver that we use here.
We then examine future tsunami hazard from the Makran subduction zone in the Western Indian Ocean. Since tsunamis present a high risk to ports in the form of high velocities and vorticity, we capture these phenomena in high resolution (down to 10m) using carefully constructed unstructured meshes for the port of Karachi. The seabed deformations triggered by the earthquake sources vary in magnitude. A parametrization of these sources is done via geometric descriptions and a newly introduced amplification parameter of the vertical deformation due the sediments. A emulator approximates the functional relationship between inputs and outputs maximum velocity and free surface elevation. A hazard assessment is performed using the emulator. Finally, we create emulators that respect the nature of time series outputs. We introduce here a novel statistical emulation of the input-output dependence of these computer models: functional registration and Functional Principal Components techniques improve the predictions of the emulator. Our phase registration method captures fine variations in amplitude. Smoothness in the time series of outputs is modelled, and we are thus able to select more representative, and more parsimonious, regression functions than a fixed basis method such as a Fourier basis. We apply this approach to the high resolution tsunami wave propagation and coastal inundation for the Cascadia region in the Pacific Northwest.

第168回 第1部
日時: 2019年5月20日(月)、13:00 - 13:35
場所: R-CCS 1階セミナー室

※ 第168回のR-CCS Cafeは、第1回 LBNL/R-CCS ワークショップ New Frontiers of Computer Architecture and System Software towards Post-Moore Era の招待講演として開催されます。

・招待講演2: Bandwidth Steering in HPC using Silicon Nanophotonics
・講演者: George Michelogiannakis (Lawrence Berkeley National Laboratory)
※発表・スライド共に英語

講演要旨: 詳細を見る

Communication is threatening to become an increasing bottleneck towards performance scaling in the post exascale era as bytes-per-FLOP ratios continue to decline. We describe bandwidth steering in HPC to take advantage of emerging photonic switches for efficiently changing the connectivity of the lower layers in a hierarchical topology to reconstruct locality that was lost from system fragmentation and was impossible to recover with task placement. This allows for more aggressive oversubscription of the higher layers to reduce cost with no performance penalty. We demonstrate bandwidth steering with a scalable algorithm in an experimental testbed and at system scale using simulations. At the system scale, bandwidth steering reduces static power consumption per unit throughput by 51% and dynamic power consumption by 10% compared to a reference topology. In addition, bandwidth steering reduces average network latency by up to 87% and improves the average throughput by an average of 4.3x.

第168回 第2部
日時: 2019年5月20日(月)、13:35 - 14:10
場所: R-CCS 1階セミナー室

・招待講演3: qFirm: Digital Firmware for Classical Control of Qubits
・講演者: Farzad Fatollahi-Fard (Lawrence Berkeley National Laboratory)
※発表・スライド共に英語

講演要旨: 詳細を見る

As the field of Quantum Computing grows, various levels of abstraction must be developed to make it easier for users to adopt. Sitting in between a control processor and the digital/analog interface for a classical control system, we propose a layer called qFirm. This layer will provide the vital interface for converting quantum instructions into the analog signals sent to control the quantum device, as well as reading the results of the device. This will provide the essential glue logic for the classical control stack for a quantum control system.

第168回 第3部
日時: 2019年5月20日(月)、14:10 - 14:45
場所: R-CCS 1階セミナー室

・招待講演4:Extending Classical Processors to Support Future Large Scale Quantum Accelerators
・講演者: Butko Anastasiia (Lawrence Berkeley National Laboratory)
※発表・スライド共に英語

講演要旨: 詳細を見る

Extensive research in material science together with outstanding engineering efforts allowed quantum technology to be significantly improved hence enabling continuing scaling of quantum circuit size. However, quantum circuit scaling itself does not guarantee any practical use without appropriate progress on the part of classical control hardware and software. To operate such a large-scale universal quantum computer with thousands of qubits, extensive classical computational resources will be required. Control hardware includes multiple layers each of which is responsible for a specific set of tasks, e.g. controllers, digital-analogue and analogue-digital converters, filters, waveform generators, etc. At this early stage of quantum architecture development, there is no clear understanding of where the upcoming challenges will be addressed through the entire stack of complex digital and analogue circuits. However, we expect that control processor will become a crucial part for successful implementation and adoption of future quantum computers.
In our talk, we discuss the challenges that classical processors will face while controlling future large-scale quantum systems. We discuss how these challenges will affect processor micro-architecture to guarantee on time quantum gate execution, continuing qubit state measurement, store and analysis, support massive parallelism and perform advanced bit manipulations on the top of the measured data.

第168回 第4部
日時: 2019年5月20日(月)、15:05 - 15:40
場所: R-CCS 1階セミナー室

・招待講演5:How open source designs will drive the next generation of HPC Systems
・講演者: David Daniel Donofrio (Lawrence Berkeley National Laboratory)
※発表・スライド共に英語

講演要旨: 詳細を見る

As we approach the end of Moore’s law modern, complex, HPC systems are increasingly relying upon specialized accelerators in order to deliver continued performance increases for specific computational workloads. Developers of these accelerators, especially in in many low volume scientific applications, face a stark choice: spend millions on a commercial license for processors and other IP, or face the significant risk and of developing custom hardware. Rapid prototyping methods need to be explored in order to make the design, verification and programming tools for these new accelerators more accessible to the broader scientific community. To increase access and innovation while reducing cost there has been a consistent march towards open source solutions for each of these components including Facebook’s Open Compute Project and Intel’s OpenHPC effort, as well as a burgeoning community surrounding RISC-V based processors.
Looking beyond accelerators that may be tightly integrated with HPC systems we see opportunities for open source hardware to include programmable logic embedded within high performance sensors and detectors for aggressive data reduction or being used in conjunction with FPGA and other reconfigurable computing based platforms. This talk will explore the emerging open source hardware effort as well as showcase new platforms for the rapid generation of future HPC accelerators.