The 140th R-CCS Cafe - part 1

To Survive the forthcoming post-Moore era, we need to innovate computer architectures in order to overcome various device constrains for successive improvement of computational performance and capability. In the processor research team, we research and develop an FPGA (Field-Programmable Gate Array)-based system which is based on the data-flow computing model.
Data-flow computing has been re-spotlighted and considered as one of the promising approaches to further scale computational performance once the multi-core scaling becomes difficult in improving performance. This is because data-flow computing can provide availability of naturally-grained parallelism and constant complexity of communication and synchronization especially when data-flow is statically mapped onto hardware.
In this talk, in addition to introduction of our team, ultimate research goals, and needs/seeds for collaboration opportunities, I talk about the FPGA-based prototype system, the data-flow compiler, and the case study of FPGA-based Tsunami Simulation, following recent trends in FPGA devices and researches for high-performance computing.